1. Field of the Invention
This invention relates generally to data processing devices and, more particularly, to a data processing device for effecting digital information processing by using a large-capacity memory.
2. Description of the Related Art
Recently, the bit unit cost of memories is greatly reduced, and apparatus which are manufactured at comparatively low costs for home or personal use but which have large-capacity memories such as field or frame memories for video signal processing are therefore increasing.
FIG. 1 schematically shows the arrangement of a conventional video signal processing circuit having such a large-capacity memory. This arrangement includes an analog video signal input terminal 100, an A/D converter 101 for digitizing an input analog video signal, a signal processing circuit 102 for processing the digitized video signal, a D/A converter 103 for converting the digital video signal processed by the signal processing circuit 102 into an analog signal, a field memory 104 for effecting digital signal exchange with the signal processing circuit 102, a sync separation circuit 105 for separating a sync signal from the digital video signal supplied from the A/D converter 101, and a memory control circuit 106 for controlling the timing of write and read operations of the field memory 104 by the timing in accordance with the sync signal separated by the sync separation circuit 105.
In the arrangement shown in FIG. 1, various kinds of processing can be performed by selecting the construction of the signal processing circuit 102 and write/read patterns for the field memory 104. In a VTR system, for example, special reproduction such as still reproduction or slow reproduction can be performed based on intermittently writing and continuously reading. Also, noise reduction processing of a field cycle type or composition processing using the image corresponding to the output from the A/D converter 101 and the image corresponding to the output from the field memory 104 can be performed based on continuously performing both write and read. The composition processing is, for example, wipe or fade processing.
Examples of systems for effecting these kinds of processing are known; an example of the above special reproduction is disclosed in Japanese Patent Application No. Sho 61-217030, an example of noise reduction processing is disclosed in Japanese Patent Application No. Sho 63-16895, and an example of composition processing is disclosed in Japanese Patent Application No. Sho 63-273356 (already filed for USP). Details of these systems will not be described in this specification because the internal arrangement of the signal processing circuit 102 does not directly relate to the present invention.
In the above-described arrangement, a capacity of 8 (bits).times.256 k (samples)=2M (bits) is needed for storing television signals such as NTSC signals or PAL signals in the field memory 104 without substantial deterioration of the signal. Although the development of large-capacity memories promoted recently has reduced the unit cost, the price of memories having a capacity of 2 Mbits is high and it is rather difficult to use such a memory for home or personal apparatus.